System on Chip (SoC) is a concept that strives to integrate more and more functionality into a given device. This integration can take the form of either hardware or software solution. Performance gains are traditionally achieved by increased clock rates and more advanced process nodes. Many SoC designs pair a digital signal processor (DSP) with a reduced instruction set computing (RISC) processor to target specific applications. A more recent approach to increasing performance has been to create multi-core devices.
Complex SoCs may include a scalable and convenient method of connecting a variety of peripheral blocks such as processors, accelerators, shared memory and IO devices while addressing the power, performance and cost requirements of the end application. Due to the complexity and high performance requirements of these devices, the chip interconnect tends to be hierarchical and partitioned depending on the latency tolerance and bandwidth requirements of the endpoints.
A typical remote trace data receiver is coupled to a system under test using a diagnostic interface and records trace data generated by one or more trace sources. It generally has enough memory to store large quantities of trace data. The trace data is stored in a “trace buffer” that is circular in nature. Once the trace buffer is full, trace recording either stops or the buffer pointer wraps with the storing of new data over the oldest previously recorded trace data. The trace buffer content may be accessed by a host computer after the storing of trace data has been stopped. Some trace receivers allow the reading of trace data already recorded while the recording of additional trace data continues.
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.